Mostrando 10 resultados de: 80
Publisher
Solid-State Electronics(9)
IEEE Transactions on Electron Devices(6)
IEEE Transactions on Circuits and Systems II: Express Briefs(5)
Microelectronic Engineering(5)
International Journal of Circuit Theory and Applications(4)
Área temáticas
Física aplicada(68)
Ciencias de la computación(17)
Ingeniería y operaciones afines(5)
Instrumentos de precisión y otros dispositivos(5)
Electricidad y electrónica(4)
Characterization and Modeling of BTI in SiC MOSFETs
Conference ObjectAbstract: SiC power MOSFETs have been investigated by performing two different kinds of measurements, the hystPalabras claves:Autores:Consentino G., Cornigli D., Crupi F., Fiegna C., Reggiani S., Sánchez Luis, Sangiorgi E., Tallarico A.N., Valdivieso C.Fuentes:scopusCompact Modeling of Perpendicular STT-MTJs with Double Reference Layers
ArticleAbstract: This paper shows the steps to set up a simulation framework for perpendicular spin-transfer torque (Palabras claves:compact model, Double-barrier MTJ, non-volatile flip-flop (NVFF), STT switchingAutores:Carpentieri M., Crupi F., D'Aquino M., Finocchio G., Marco Lanuzza, Rose R.D.Fuentes:scopusAssessment of 2D-FET Based Digital and Analog Circuits on Paper
ArticleAbstract: Two-dimensional (2D) materials represent an emerging technology for transistor electronics in view oPalabras claves:2d materials, Field-Effect Transistor (FET), Molybdenum disulfide (MoS ) 2, Paper electronics, Verilog-A modelAutores:Crupi F., Iannaccone G., Marco Lanuzza, Rose R.D., Vatalaro M.Fuentes:scopusAssessment of InAs/AlGaSb Tunnel-FET Virtual Technology Platform for Low-Power Digital Circuits
ArticleAbstract: In this work, a complementary InAs/Al0.05Ga0.95Sb tunnel field-effect-Transistor (TFET) virtual techPalabras claves:full-Adder, III-V, tunnel field effect transistor (TFET), very large scale integration (VLSI).Autores:Crupi F., Esseni D., Marco Lanuzza, Palestri P., Selmi L., Strangio S.Fuentes:scopusAssessment of STT-MRAM performance at nanoscaled technology nodes using a device-to-memory simulation framework
ArticleAbstract: This paper deals with the technology scalability of spin-transfer torque magnetic RAMs (STT-MRAMs)baPalabras claves:Device-to-memory analysis, FinFET, Magnetic tunnel junction (MTJ), STT-MRAM, technology scalingAutores:Crupi F., Esteban Garzón, Marco Lanuzza, Rose R.D., Trojman L.Fuentes:scopusAssessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework
ArticleAbstract: This paper explores non-volatile cache memories implemented by spin-transfer torque magnetic randomPalabras claves:cache memory, Device-to-system simulation framework, double-barrier magnetic tunnel junction (DMTJ), FinFET, STT-MRAMAutores:Carpentieri M., Crupi F., Esteban Garzón, Finocchio G., Marco Lanuzza, Rose R.D., Trojman L.Fuentes:scopusAssessment of paper-based MoS<inf>2</inf> FET for Physically Unclonable Functions
ArticleAbstract: Two-dimensional (2D) materials are recognized as a promising beyond-CMOS technology thanks to theirPalabras claves:2d materials, Hardware security, Molybdenum disulfide (MoS ) 2, Paper electronics, physically unclonable function (PUF), Verilog-A modelAutores:Conti S., Crupi F., Iannaccone G., Magnone P., Marco Lanuzza, Rose R.D., Vatalaro M.Fuentes:scopusBTI saturation and universal relaxation in SiC power MOSFETs
ArticleAbstract: This work focuses on the positive bias temperature instability of SiC-based MOSFETs under differentPalabras claves:de-trapping, PBTI, recovery, SiC, TRAPPING, Universal relaxation, Zafar's modelAutores:Crupi F., Eliana Acurio, Meneghesso G., Reggiani S., Sánchez LuisFuentes:scopusBenchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits
ArticleAbstract: In this work, a benchmark for low-power digital applications of a III-V TFET technology platform agaPalabras claves:Full adders, III-V, Ripple carry adders, TFETAutores:Crupi F., Esseni D., Marco Lanuzza, Palestri P., Selmi L., Strangio S.Fuentes:scopusAn energy aware variation-tolerant writing termination control for STT-based non volatile flip-flops
Conference ObjectAbstract: In this paper, we propose a variation-tolerant design methodology to embed self-write termination coPalabras claves:digital circuits, Energy efficiency, Non-volatile flip-flop, STT-MRAM, VLSI, Zero-leakage circuitsAutores:Alioto M., Crupi F., Marco Lanuzza, Rose R.D.Fuentes:scopus