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Hybrid clock recovery for a gigabit POF transceiver implemented on FPGA
ArticleAbstract: In this paper, we present a clock recovery system implemented on field programmable gate array and iPalabras claves:Clock recovery (CR), DSP, Field programmable gate array (FPGA), Gigabit Ethernet, Optical Communications, phase-locked loop (PLL), Polymer Optical Fiber, timing error detector (TED)Autores:Abrate S., Nespola A., Ramirez J., Roberto Gaudino, Savio P., Straullu S.Fuentes:scopusTowards a new Gigabit Ethernet PHY for SI-POF
Conference ObjectAbstract: This paper presents a proposal for a new PHY to implement Gigabit Ethernet over SI-POF. The block diPalabras claves:Autores:Abrate S., Nespola A., Ramirez J., Roberto Gaudino, Savio P., Straullu S., Zeolla D.Fuentes:scopus