Mostrando 10 resultados de: 11
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6th FPGAworld Conference, Academic Proceedings 2009(2)
10th International Symposium on Reconfigurable and Communication-centric Systems-on-Chip, ReCoSoC 2015(1)
2009 NORCHIP(1)
2013 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2013(1)
2014 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2014(1)
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Ciencias de la computación(9)
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Origen
scopus(11)
A formal, model-driven design flow for system simulation and multi-core implementation
Conference ObjectAbstract: With the growing complexity of Real-Time Embedded Systems (RTES), there is a huge interest in usingPalabras claves:Computational modeling, Embedded Systems, Engines, Libraries, process control, semantics, Unified modeling languageAutores:Champeau J., Diallo P.I., Ingo Sander, Niaki S.H.A., Öberg J., Robino F.Fuentes:scopusCamera and LCM IP-Cores for NIOS SOPC system
Conference ObjectAbstract: This paper presents the development of IP-Cores to integrate the Terasic DC2 Camera and LCM (LCD ModPalabras claves:Embedded Systems, Fpga, IMAGE PROCESSING, IP-core, SOCAutores:BYRON NAVAS, Ingo Sander, Öberg J.Fuentes:scopusDesign and implementation of a plesiochronous multi-core 4x4 network-on-chip FPGA platform with MPI HAL support
Conference ObjectAbstract: The Multi-Core NoC is a 4 by 4 Mesh NoC targeted for Altera FPGAs. It implements a deflective routinPalabras claves:Altera, Fpga, hardware platform, MPI, MPSoC, Multi-core, Noc, PlesiochronousAutores:Ingo Sander, Minhass W.H., Öberg J.Fuentes:scopusExploring power and throughput for dataflow applications on pbkp_redictable NoC multiprocessors
Conference ObjectAbstract: System level optimization for multiple mixed-criticality applications on shared networked multiprocePalabras claves:constraint programming, Design space exploration, Mixed criticality system, Multiprocessor system on chip, Network on chip, System level design, Temporally disjoint networkAutores:Ingo Sander, Mohammadat T., Öberg J., Rosvall K., Ungureanu G.Fuentes:scopusOn providing scalable self-healing adaptive fault-tolerance to RTR SoCs
Conference ObjectAbstract: The dependability of heterogeneous many-core FPGA based systems are threatened by higher failure ratPalabras claves:Autores:BYRON NAVAS, Ingo Sander, Öberg J.Fuentes:scopusImplementation of a scalable, globally plesiochronous locally synchronous, off-chip NoC communication protocol
Conference ObjectAbstract: Multiprocessor system-on-chip design (MPSoC) is becoming a regular feature of the embedded systems.Palabras claves:Autores:Ingo Sander, Minhass W.H., Öberg J.Fuentes:scopusTowards cognitive reconfigurable hardware: Self-Aware learning in RTR fault-Tolerant SoCs
Conference ObjectAbstract: Traditional embedded systems are evolving into power-And-performance-domain self-Aware intelligent sPalabras claves:Cognitive hardware, Complex adaptive systems, Dynamic fault-Tolerance, Fpga, Machine learning, Partial and run-Time reconfiguration, self-awareness, self-healingAutores:BYRON NAVAS, Ingo Sander, Öberg J.Fuentes:scopusTowards the generic reconfigurable accelerator: Algorithm development, core design, and performance analysis
Conference ObjectAbstract: Adoption of reconfigurable computing is limited in part by the lack of simplified, economic, and reuPalabras claves:Algorithm development, Design methodology, Embedded System, Hardware accelerator, Partial and run-Time reconfiguration, Reconfiguration techniques, System-on-chipAutores:BYRON NAVAS, Ingo Sander, Öberg J.Fuentes:scopusSAFEPOWER project: Architecture for safe and power-efficient mixed-criticality systems
ArticleAbstract: With the ever increasing industrial demand for bigger, faster and more efficient systems, a growingPalabras claves:Autores:Azkarate-Askasua M., Coronel J., Crespo A., Davidmann S., Diaz Garcia J.C., Fakih M., Grüttner K., Ingo Sander, Lenz A., Maleki A., Mohammadat M.T., Öberg J., Obermaisser R., Pérez-Cerrolaza J., Romero N.G., Schreiner S., Seyyedi R., Söderquist I.Fuentes:scopusThe RecoBlock SoC platform: A flexible array of reusable run-time-reconfigurable IP-blocks
Conference ObjectAbstract: Run-time reconflgurable (RTR) FPGAs combine the flexibility of software with the high efficiency ofPalabras claves:Adaptivity, Embedded Systems, Partial and run-Time reconfiguration, Reconfigurable architectures, System-on-chipAutores:BYRON NAVAS, Ingo Sander, Öberg J.Fuentes:scopus