Compact associative memory for AER spike decoding in FPGA-based evolvable SNN emulation

Abstract:

A spike decoding scheme for Address Event Representation (AER)-based transmission in Spiking Neural Network (SNN) emulators is introduced. The proposed scheme is a modified associative memory based on an efficient use of BRAM, supporting connectivity upgrade in real-time for hardware implementations of evolutionary networks. After analysing the different options and selecting the most efficient one, a prototype example based on FPGA is provided together with a novel hashing technique to demonstrate a compact on-chip solution for implementing inter-chip connectivity in SNN.

Año de publicación:

2016

Keywords:

• Digital neuromorphic systems
• Evolvable connections
• AER
• Associative memory
• SNN

Fuente:

scopus

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