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Mostrando 10 resultados de: 132
A BLIS-like matrix multiplication for machine learning in the RISC-V ISA-based GAP8 processor
ArticleAbstract: We address the efficient realization of matrix multiplication (gemm), with application in the convolPalabras claves:high performance, Matrix multiplication, RISC-V GAP8Autores:, Castelló A., Quintana-Ortí E.S.Fuentes:scopusA Low-Energy DMTJ-Based Ternary Content- Addressable Memory With Reliable Sub-Nanosecond Search Operation
ArticleAbstract: In this paper, we propose an energy-efficient, reliable, hybrid, 10-transistor/2-Double-Barrier-MagnPalabras claves:Double-barrier MTJ, energy-efficiency, Low-power, non-volatile TCAM (NV-TCAM)Autores:Carpentieri M., Esteban Garzón, Finocchio G., Marco Lanuzza, Teman A., Yavits L.Fuentes:scopusA New optimized high-speed low-power Data-Driven Dynamic (D3L) 32-bit Kogge-Stone adder
Conference ObjectAbstract: Data Driven Dynamic Logic (D3L) achieves a considerably energy saving, over conventional Domino LogiPalabras claves:D3L, Data pre-charged dynamic logic, Parallel prefix adderAutores:Frustaci F., Marco LanuzzaFuentes:scopusA PCI AER Co-Processor Evaluation Based on CPUs Performance Counters
OtherAbstract: Image processing in digital computer systems usually considers the visual information as a sequencePalabras claves:Autores:Gabriel MorenoFuentes:googleA RISC-V-based Research Platform for Rapid Design Cycle
Conference ObjectAbstract: This work proposes a novel platform for bringing a project from the concept to the tapeout stage inPalabras claves:Autores:Esteban Garzón, Golman R., Harel O., Kra Y., Marco Lanuzza, Noy T., Pollock A., Rudin Y., Shoshan Y., Teman A., Weitzman Y., Yuzhaninov S.Fuentes:scopusA cache coherence protocol for distributed memory platforms
ArticleAbstract: This work proposes a Cache Memory protocol that manages the coherence for systems with distributed mPalabras claves:cache memory, Coherence protocols, Distributed memory systemsAutores:José Lisandro Aguilar Castro, Sumoza R.Fuentes:scopusA composable and predictable MPSoC design flow for multiple real-time applications
Book PartAbstract: Design of real-time MPSoC systems including multiple applications is challenging because temporal rePalabras claves:Autores:Altinel E., Goossens K., Ingo Sander, Koedam M., Molnos A., Niaki S.H.A.Fuentes:scopusA constraint-based design space exploration framework for real-time applications on MPSoCs
Conference ObjectAbstract: Design space exploration (DSE) is a critical step in the design process of real-time multiprocessorPalabras claves:Autores:Ingo Sander, Rosvall K.Fuentes:scopusA deep analysis of SEU consequences in the internal memory of LEON3 processor
Conference ObjectAbstract: This paper presents an analysis of the effects of Single Event Upset (SEU) into the internal memoryPalabras claves:Autores:Bouesse F., Hadj W.E., Kchaou A., Pablo F. Ramos, PABLO FRANCISCO RAMOS VARGAS, Tourki R., Velazco R.Fuentes:googlescopusA fast modular exponentiation for RSA on systolic arrays
OtherAbstract: This paper presents two systolic algorithms for modular exponentiations based on a k-SR representatiPalabras claves:Autores:Marcel VillavicencioFuentes:google