Mostrando 10 resultados de: 35
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International Journal of Circuit Theory and Applications(4)
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scopus(35)
Comparative analysis of yield optimized pulsed flip-flops
ArticleAbstract: In this paper, the influence of random process variations on pulsed flip-flops is analyzed. Monte CaPalabras claves:Autores:Corsonello P., Frustaci F., Marco Lanuzza, Perri S., Rose R.D.Fuentes:scopusAn efficient and low-cost design methodology to improve SRAM-Based FPGA robustness in space and avionics applications
Conference ObjectAbstract: This paper presents an efficient approach to protect an FPGA design against Single Event Upsets (SEUPalabras claves:Avionics, Fpga, Reconfigurable System, Single Event Upsets, spaceAutores:Corsonello P., Frustaci F., Marco Lanuzza, Perri S., Zicari P.Fuentes:scopusAn efficient wavelet image encoder for FPGA-based designs
Conference ObjectAbstract: This paper presents the design of a new wavelet-based encoder suitable for fast and low-power imagePalabras claves:Autores:Cocorullo G., Corsonello P., Marco Lanuzza, Perri S.Fuentes:scopusAnalyzing noise robustness of wide fan-in dynamic logic gates under process variations
ArticleAbstract: Wide fan-in dynamic logic gates are difficult to design due to the large number of leaky evaluationPalabras claves:Dynamic logic, process variations, wide fan-inAutores:Corsonello P., Frustaci F., Marco Lanuzza, Perri S.Fuentes:scopusA high-performance fully reconfigurable FPGA-based 2D convolution processor
ArticleAbstract: This paper presents a new fully reconfigurable 2D convolver designed for FPGA-based image and videoPalabras claves:Convolution, IMAGE PROCESSING, Single instruction multiple data circuitsAutores:Cocorullo G., Corsonello P., Marco Lanuzza, Perri S.Fuentes:scopusA new low-power high-speed single-clock-cycle binary comparator
Conference ObjectAbstract: This paper presents a new ultra-low power high-speed single-clock-cycle binary comparator. It is basPalabras claves:Autores:Corsonello P., Frustaci F., Marco Lanuzza, Perri S.Fuentes:scopusA new reconfigurable coarse-grain architecture for multimedia applications
Conference ObjectAbstract: This paper presents MORA, a new coarse-grain reconfigurable architecture optimized for multimedia prPalabras claves:Autores:Corsonello P., Marco Lanuzza, Margala M., Perri S.Fuentes:scopusA novel background subtraction method based on color invariants and grayscale levels
Conference ObjectAbstract: This paper presents a new method for background subtraction which takes advantages of using the coloPalabras claves:automatic monitoring, Background subtraction, Video systemsAutores:Cocorullo G., Corsonello P., Frustaci F., Lorena Guachi-Guachi, Perri S.Fuentes:scopusA self-hosting configuration management system to mitigate the impact of radiation-induced multi-bit upsets in SRAM-Based FPGAs
Conference ObjectAbstract: This paper presents an efficient circuit to mitigate the impact of Radiation-Induced Multi-Bit UpsetPalabras claves:Autores:Corsonello P., Frustaci F., Marco Lanuzza, Perri S., Zicari P.Fuentes:scopusCost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications
Conference ObjectAbstract: Multimedia applications have become a dominant computing workload for computer systems as well as foPalabras claves:Datapath, Processor-In-Memory, reconfigurable computingAutores:Corsonello P., Marco Lanuzza, Margala M.Fuentes:scopus