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International Journal of Circuit Theory and Applications(3)
IEEE Transactions on Circuits and Systems II: Express Briefs(1)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems(1)
IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation(1)
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scopus(15)
An efficient wavelet image encoder for FPGA-based designs
Conference ObjectAbstract: This paper presents the design of a new wavelet-based encoder suitable for fast and low-power imagePalabras claves:Autores:Cocorullo G., Corsonello P., Marco Lanuzza, Perri S.Fuentes:scopusAnalyzing noise robustness of wide fan-in dynamic logic gates under process variations
ArticleAbstract: Wide fan-in dynamic logic gates are difficult to design due to the large number of leaky evaluationPalabras claves:Dynamic logic, process variations, wide fan-inAutores:Corsonello P., Frustaci F., Marco Lanuzza, Perri S.Fuentes:scopusA high-performance fully reconfigurable FPGA-based 2D convolution processor
ArticleAbstract: This paper presents a new fully reconfigurable 2D convolver designed for FPGA-based image and videoPalabras claves:Convolution, IMAGE PROCESSING, Single instruction multiple data circuitsAutores:Cocorullo G., Corsonello P., Marco Lanuzza, Perri S.Fuentes:scopusA new reconfigurable coarse-grain architecture for multimedia applications
Conference ObjectAbstract: This paper presents MORA, a new coarse-grain reconfigurable architecture optimized for multimedia prPalabras claves:Autores:Corsonello P., Marco Lanuzza, Margala M., Perri S.Fuentes:scopusCost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications
Conference ObjectAbstract: Multimedia applications have become a dominant computing workload for computer systems as well as foPalabras claves:Datapath, Processor-In-Memory, reconfigurable computingAutores:Corsonello P., Marco Lanuzza, Margala M.Fuentes:scopusDesign and evaluation of an energy-delay-area efficient datapath for coarse-grain reconfigurable computing systems
ArticleAbstract: This paper presents the architecture and complete VLSI implementation of a high data throughput, enePalabras claves:arithmetic circuits, Data path design, Reconfigurable architecturesAutores:Corsonello P., Marco Lanuzza, Margate M., Perri S., Purohit S.Fuentes:scopusDesign and implementation of a 90nm low bit-rate image compression core
Conference ObjectAbstract: This paper presents a low-cost, high throughput Discrete Wavelet Transform-based image compressor. TPalabras claves:Autores:Cocorullo G., Corsonello P., Marco Lanuzza, Perri S., Staino G.Fuentes:scopusDesign of high-speed low-power parallel-prefix adder trees in nanometer technologies
ArticleAbstract: This paper presents a novel approach to design high-speed low-power parallel-prefix adder trees. SubPalabras claves:Brent-Kung adder tree, High-speed addition, Parallel-Prefix addersAutores:Corsonello P., Marco Lanuzza, Perri S.Fuentes:scopusDesign-space exploration of energy-delay-area efficient coarse-grain reconfigurable datapath
Conference ObjectAbstract: This paper presents the VLSI design of a high data throughput, energy and area efficient data path tPalabras claves:Autores:Corsonello P., Marco Lanuzza, Margala M., Perri S., Purohit S.Fuentes:scopusDesigning high-speed adders in power-constrained environments
ArticleAbstract: Data-driven dynamic logic (D3L) is very efficient when low-power constraints are mandatory. UnfortunPalabras claves:Clock-precharged dynamic logic, Data-driven dynamic logic (D3L), Data-precharged dynamic logic, Parallel prefix adderAutores:Corsonello P., Frustaci F., Marco Lanuzza, Perri S., Zicari P.Fuentes:scopus