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Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)(3)
2018 IEEE 3rd Ecuador Technical Chapters Meeting, ETCM 2018(1)
2018 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2018(1)
ICECS 2020 - 27th IEEE International Conference on Electronics, Circuits and Systems, Proceedings(1)
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scopus(9)
Compact associative memory for AER spike decoding in FPGA-based evolvable SNN emulation
Conference ObjectAbstract: A spike decoding scheme for Address Event Representation (AER)-based transmission in Spiking NeuralPalabras claves:AER, Associative memory, Digital neuromorphic systems, Evolvable connections, SNNAutores:Madrenas J., Mireya Zapata-RodríguezFuentes:googlescopusAER-SRT: Scalable spike distribution by means of synchronous serial ring topology address event representation
ArticleAbstract: Given the massive number of interconnects in Spiking Neural Networks (SNNs), distributing spikes effPalabras claves:AER (Address Event Representation), Aurora protocol, Multi-chip communication, SNN emulation, Synchronous serial ring, Time slot emulationAutores:Dorta T., Madrenas J., Mireya Zapata-Rodríguez, Sánchez G.Fuentes:googlescopusEfficient Configuration for a Scalable Spiking Neural Network Platform by means of a Synchronous Address Event Representation bus
Conference ObjectAbstract: Hardware architectures for Spiking Neural Networks (SNNs) emulation exhibit accelerated processing tPalabras claves:AER (Address Event Representation), Configurability, Fpga, multi-chip platform, PSoC, SNN emulationAutores:Janio Jadán-Guerrero, Madrenas J., Mireya Zapata-RodríguezFuentes:googlescopusHardware-software co-design for efficient and scalable real-time emulation of SNNs on the edge
Conference ObjectAbstract: This paper introduces a novel workflow for Distributed Spiking Neural Network Architecture (DSNA). APalabras claves:Edge computing, Hardware-Software Integration, HEENS, Neural Computing, SNAVA, SNN, Spiking Neural NetworksAutores:Bernardo Vallejo-Mancero, Madrenas J., Mata-Hernandez D., Mireya Zapata-Rodríguez, Oltra-Oltra J.A., Sato S.Fuentes:googlescopusPSoC-Based Real-Time Data Acquisition for a Scalable Spiking Neural Network Hardware Architecture
Conference ObjectAbstract: Data acquisition for monitoring the spiky activity of large-scale SNN hardware architectures are a cPalabras claves:data-Acquisition, Monitoring, SOC, Spiking Neural Networks, ZYNQAutores:Balaji U.K., Madrenas J., Mireya Zapata-RodríguezFuentes:googlescopusTowards efficient and adaptive cyber physical spiking neural integrated systems
Conference ObjectAbstract: This work introduces multi-sensor integration combined with an efficient and adaptive Spiking NeuralPalabras claves:CMOS-MEMS, Cyber Physical Neural Systems, Integrated Sensors, Integration, MEMs, Sensor Neural Computing, SNN, Spiking Neural NetworksAutores:Cosp-Vilella J., Fernandez D., Madrenas J., Mata-Hernandez D., Mireya Zapata-Rodríguez, Oltra J.A., Sanchez-Chiva J.M., Sato S., Valle J.Fuentes:googlescopusReal-Time Display of Spiking Neural Activity of SIMD Hardware Using an HDMI Interface
Conference ObjectAbstract: Spiking neural networks (SNN) are considered the third generation of artificial networks and are powPalabras claves:Fpga, Raster plot, Real-time HDMI display, Spiking neural networkAutores:Bernardo Vallejo-Mancero, Madrenas J., Mireya Zapata-Rodríguez, Nader C.Fuentes:googlescopusSNAVA—A real-time multi-FPGA multi-model spiking neural network simulation architecture
ArticleAbstract: Spiking Neural Networks (SNN) for Versatile Applications (SNAVA) simulation platform is a scalable aPalabras claves:Digital neural simulation, Fpga, Neuromorphic systems, SNNsAutores:Cambria S., Dorta T., Krishnamourthy K., Madrenas J., Marti A., Mireya Zapata-Rodríguez, Pirrone V., Sánchez G., Sripad A.Fuentes:googlescopusSynfire chain emulation by means of flexible SNN modeling on a SIMD multicore architecture
Conference ObjectAbstract: The implementation of a synfire chain (SFC) application that performs synchronous alignment mapped oPalabras claves:AER, Fpga, Massive parallelism, REAL TIME, SNN emulation, Time slot processingAutores:Madrenas J., Mireya Zapata-RodríguezFuentes:googlescopus