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International Journal of Circuit Theory and Applications(3)
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scopus(25)
An efficient wavelet image encoder for FPGA-based designs
Conference ObjectAbstract: This paper presents the design of a new wavelet-based encoder suitable for fast and low-power imagePalabras claves:Autores:Cocorullo G., Corsonello P., Marco Lanuzza, Perri S.Fuentes:scopusAnalyzing noise robustness of wide fan-in dynamic logic gates under process variations
ArticleAbstract: Wide fan-in dynamic logic gates are difficult to design due to the large number of leaky evaluationPalabras claves:Dynamic logic, process variations, wide fan-inAutores:Corsonello P., Frustaci F., Marco Lanuzza, Perri S.Fuentes:scopusAM<sup>4</sup>: MRAM Crossbar Based CAM/TCAM/ACAM/AP for In-Memory Computing
ArticleAbstract: In-memory computing seeks to minimize data movement and alleviate the memory wall by computing in-siPalabras claves:associative memories, associative processor, CAM, Double-barrier MTJ, emerging memories, MRAM, MTJ, Non-von Neumann computer architecture, TCAMAutores:Esteban Garzón, Marco Lanuzza, Teman A., Yavits L.Fuentes:scopusA Low-Energy DMTJ-Based Ternary Content- Addressable Memory With Reliable Sub-Nanosecond Search Operation
ArticleAbstract: In this paper, we propose an energy-efficient, reliable, hybrid, 10-transistor/2-Double-Barrier-MagnPalabras claves:Double-barrier MTJ, energy-efficiency, Low-power, non-volatile TCAM (NV-TCAM)Autores:Carpentieri M., Esteban Garzón, Finocchio G., Marco Lanuzza, Teman A., Yavits L.Fuentes:scopusA New optimized high-speed low-power Data-Driven Dynamic (D3L) 32-bit Kogge-Stone adder
Conference ObjectAbstract: Data Driven Dynamic Logic (D3L) achieves a considerably energy saving, over conventional Domino LogiPalabras claves:D3L, Data pre-charged dynamic logic, Parallel prefix adderAutores:Frustaci F., Marco LanuzzaFuentes:scopusA RISC-V-based Research Platform for Rapid Design Cycle
Conference ObjectAbstract: This work proposes a novel platform for bringing a project from the concept to the tapeout stage inPalabras claves:Autores:Esteban Garzón, Golman R., Harel O., Kra Y., Marco Lanuzza, Noy T., Pollock A., Rudin Y., Shoshan Y., Teman A., Weitzman Y., Yuzhaninov S.Fuentes:scopusA high-performance fully reconfigurable FPGA-based 2D convolution processor
ArticleAbstract: This paper presents a new fully reconfigurable 2D convolver designed for FPGA-based image and videoPalabras claves:Convolution, IMAGE PROCESSING, Single instruction multiple data circuitsAutores:Cocorullo G., Corsonello P., Marco Lanuzza, Perri S.Fuentes:scopusA new reconfigurable coarse-grain architecture for multimedia applications
Conference ObjectAbstract: This paper presents MORA, a new coarse-grain reconfigurable architecture optimized for multimedia prPalabras claves:Autores:Corsonello P., Marco Lanuzza, Margala M., Perri S.Fuentes:scopusCost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications
Conference ObjectAbstract: Multimedia applications have become a dominant computing workload for computer systems as well as foPalabras claves:Datapath, Processor-In-Memory, reconfigurable computingAutores:Corsonello P., Marco Lanuzza, Margala M.Fuentes:scopusDesign and evaluation of an energy-delay-area efficient datapath for coarse-grain reconfigurable computing systems
ArticleAbstract: This paper presents the architecture and complete VLSI implementation of a high data throughput, enePalabras claves:arithmetic circuits, Data path design, Reconfigurable architecturesAutores:Corsonello P., Marco Lanuzza, Margate M., Perri S., Purohit S.Fuentes:scopus