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scopus(9)
A RISC-V-based Research Platform for Rapid Design Cycle
Conference ObjectAbstract: This work proposes a novel platform for bringing a project from the concept to the tapeout stage inPalabras claves:Autores:Esteban Garzón, Golman R., Harel O., Kra Y., Marco Lanuzza, Noy T., Pollock A., Rudin Y., Shoshan Y., Teman A., Weitzman Y., Yuzhaninov S.Fuentes:scopusA variation-aware simulation framework for hybrid CMOS/spintronic circuits
Conference ObjectAbstract: In this paper, a variation-aware simulation framework is introduced for hybrid circuits comprising MPalabras claves:device-circuit simulation, magnetic memory, Spintronic circuits, variationsAutores:Alioto M., Carpentieri M., Crupi F., Finocchio G., Marco Lanuzza, Rose R.D., Siracusano G., Tomasello R.Fuentes:scopusExploiting single-well design for energy-efficient ultra-wide voltage range Dual Mode Logic -based digital circuits in 28nm FD-SOI technology
Conference ObjectAbstract: In this paper we evaluate the implementation options of energy-efficient dual mode logic (DML) circuPalabras claves:Adaptive energy-efficient digital design, Dual mode logic, FD-SOIAutores:Fish A., Marco Lanuzza, Ramiro Taco, Shavit N., Stanger I., Yavits L.Fuentes:scopusExtended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology
Conference ObjectAbstract: Recently, we proposed a low-granularity back-bias control technique [1] optimized for the ultra-thinPalabras claves:28nm UTBB FD-SOI, Dynamic body biasing, low voltage designAutores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopusEvaluation of Dual Mode Logic in 28nm FD-SOI technology
Conference ObjectAbstract: For the first time, the Dual Mode Logic (DML) technique is evaluated in 28 nm UTBB FD-SOI technologyPalabras claves:dual mode logic (DML), Low PowerAutores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopusLive Demo: Silicon evaluation of multimode dual mode logic for PVT-aware datapaths
Conference ObjectAbstract: This demo demonstrates the unique capabilities of the multimode Dual Mode Logic (DML) design techniqPalabras claves:Autores:Fish A., Marco Lanuzza, Ramiro Taco, Shavit N., Stanger I.Fuentes:scopusLive demo: An 88FJ / 40 MHz [0.4V] - 0.61PJ / 1GHz [0.9V] dual mode logic 8x8-bit multiplier accumulator with a self-adjustment mechanism in 28 nm FD-SOI
Conference ObjectAbstract: The unique ability of dual mode logic (DML) to self-adapt to computational needs by providing high sPalabras claves:Autores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopusLive demonstration: A 0.8V, 1.54 pJ / 940 MHz dual mode logic-based 16x16-bit booth multiplier in 16-nm FinFET
Conference ObjectAbstract: The Dual Mode Logic (DML) defines run-time adaptive digital architectures that switch to either imprPalabras claves:Autores:Fish A., Marco Lanuzza, Ramiro Taco, Shavit N., Stanger I.Fuentes:scopusRobust dual mode pass logic (DMPL) for energy efficiency and high performance
Conference ObjectAbstract: In the past, Pass Transistor Logic (PTL) was widely used due to benefits in terms of speed and powerPalabras claves:16 nm, dual mode logic (DML), Energy efficiency, Logic family, Low Power, Pass Transistor Logic (PTL)Autores:Fish A., Marco Lanuzza, Ramiro Taco, Shavit N., Stanger I., Yavits L.Fuentes:scopus