Mostrando 10 resultados de: 18
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Proceedings - IEEE International Symposium on Circuits and Systems(3)
2020 IEEE ANDESCON, ANDESCON 2020(2)
Electronics (Switzerland)(2)
2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings(1)
2018 IEEE International Conference on the Science of Electrical Engineering in Israel, ICSEE 2018(1)
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Física aplicada(8)
Economía(1)
Ingeniería y operaciones afines(1)
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720p-HD Gray-scale and Color Images Shape Recognition System Implementation on an FPGA Platform with a 1080pFull-HD HDMI Interface using a Hu Moments Algorithm
Conference ObjectAbstract: The present work implements and adapts a fast shape recognition algorithm on the Xilinx VC707 VIRTEXPalabras claves:ADV7511, Fpga, Full-HD, Gray Scale, HDL, HDMI, IIC, RGB, Shape recognitionAutores:André Borja, Daniel Cárdenas, Felipe Toscano, Luis Miguel Prócel Moya, Ramiro Taco, Trojman L.Fuentes:scopusDMTJ-Based Non-Volatile Ternary Content Addressable Memory for Energy-Efficient High-Performance Systems
Conference ObjectAbstract: This paper explores performance of non-volatile ternary content addressable memories (NV-TCAMs), expPalabras claves:Double-barrier magnetic tunnel junction, energy-efficiency, Ternary content-addressable memoriesAutores:Kevin Vicuña, Luis Miguel Prócel Moya, Ramiro Taco, Trojman L.Fuentes:googlescopusAn 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] dual-mode logic 8 × 8 bit multiplier accumulator with a self-adjustment mechanism in 28-nm FD-SOI
ArticleAbstract: The unique ability of dual-mode logic (DML) to self-adapt to computational needs by providing high sPalabras claves:Dual-mode logic (DML), high-speed, Low-power, self-adaptive multiply-accumulate (MAC)Autores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopusFlexDML: High Utilization Configurable Multimode Arithmetic Units Featuring Dual Mode Logic
ArticleAbstract: Dual mode logic (DML) enables flexible energy-delay (ED) optimization. By setting the design elementPalabras claves:Arithmetic, CMOS, configurable computing, DML, dual mode logic (DML), dynamic, mixed-mode, Pipeline, staticAutores:Fish A., Levi I., Marco Lanuzza, Ramiro Taco, Shavit N., Stanger I., Yavits L.Fuentes:scopusEnergy efficient self-adaptive dual mode logic address decoder
ArticleAbstract: This paper presents a 1024-bit self-adaptive memory address decoder based on Dual Mode Logic (DML) dPalabras claves:Address decoder, Controller, Dual mode logic, Self-adaptiveAutores:Ariana Musello, Cristhopher Mosquera, Esteban Garzón, Kevin Vicuña, Luis Miguel Prócel Moya, Mateo Rendón, Ramiro Taco, Sara Benedictis, Trojman L.Fuentes:googlescopusEvaluation of Dual Mode Logic in 28nm FD-SOI technology
Conference ObjectAbstract: For the first time, the Dual Mode Logic (DML) technique is evaluated in 28 nm UTBB FD-SOI technologyPalabras claves:dual mode logic (DML), Low PowerAutores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopusDynamic gate-level body biasing for subthreshold digital design
Conference ObjectAbstract: Dynamic gate-level body biasing has been recently proposed as an alternative design methodology forPalabras claves:Autores:Albano D., Marco Lanuzza, Ramiro TacoFuentes:scopusEffects of the technology scaling down to 28nm on Ultra-Low Voltage and Power OTA performance using TCAD simulations
Conference ObjectAbstract: In this paper, the effect on the performances of the technology scaling down to 28nm (bulk and planaPalabras claves:28nm, 90nm, Feed Forward rejection, OTA, PDK, Pseudo Differential Pair, TCAD simulation, Ultra-low power, Ultra-low voltageAutores:André Borja, Juan Orozco, Luis Miguel Prócel Moya, Mateo Bonilla, Mateo Valencia, Ramiro Taco, Trojman L.Fuentes:scopusEfficiency of Dual Mode Logic in Nanoscale Technology Nodes
Conference ObjectAbstract: Previous work on Dual Mode Logic (DML) have demonstrated improvements in frequency and energy comparPalabras claves:alternative logic family, CMOS, dual mode logic (DML), nanoscaled technology nodesAutores:Fish A., Ramiro Taco, Shavit N.Fuentes:scopusHigh-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator
Conference ObjectAbstract: This paper presents an energy-efficient single-clock-cycle binary Dual-Mode Logic (DML)-based comparPalabras claves:arithmetic circuits, binary comparator, CMOS, Dual-mode logicAutores:Luis Miguel Prócel Moya, Marco Lanuzza, Ramiro Taco, Ricardo Escobar, Trojman L.Fuentes:scopus