Mostrando 10 resultados de: 18
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Proceedings - IEEE International Symposium on Circuits and Systems(3)
2020 IEEE ANDESCON, ANDESCON 2020(2)
Electronics (Switzerland)(2)
2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings(1)
2018 IEEE International Conference on the Science of Electrical Engineering in Israel, ICSEE 2018(1)
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An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] dual-mode logic 8 × 8 bit multiplier accumulator with a self-adjustment mechanism in 28-nm FD-SOI
ArticleAbstract: The unique ability of dual-mode logic (DML) to self-adapt to computational needs by providing high sPalabras claves:Dual-mode logic (DML), high-speed, Low-power, self-adaptive multiply-accumulate (MAC)Autores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopusFlexDML: High Utilization Configurable Multimode Arithmetic Units Featuring Dual Mode Logic
ArticleAbstract: Dual mode logic (DML) enables flexible energy-delay (ED) optimization. By setting the design elementPalabras claves:Arithmetic, CMOS, configurable computing, DML, dual mode logic (DML), dynamic, mixed-mode, Pipeline, staticAutores:Fish A., Levi I., Marco Lanuzza, Ramiro Taco, Shavit N., Stanger I., Yavits L.Fuentes:scopusEvaluation of Dual Mode Logic in 28nm FD-SOI technology
Conference ObjectAbstract: For the first time, the Dual Mode Logic (DML) technique is evaluated in 28 nm UTBB FD-SOI technologyPalabras claves:dual mode logic (DML), Low PowerAutores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopusDynamic gate-level body biasing for subthreshold digital design
Conference ObjectAbstract: Dynamic gate-level body biasing has been recently proposed as an alternative design methodology forPalabras claves:Autores:Albano D., Marco Lanuzza, Ramiro TacoFuentes:scopusEfficiency of Dual Mode Logic in Nanoscale Technology Nodes
Conference ObjectAbstract: Previous work on Dual Mode Logic (DML) have demonstrated improvements in frequency and energy comparPalabras claves:alternative logic family, CMOS, dual mode logic (DML), nanoscaled technology nodesAutores:Fish A., Ramiro Taco, Shavit N.Fuentes:scopusLive Demo: Silicon evaluation of multimode dual mode logic for PVT-aware datapaths
Conference ObjectAbstract: This demo demonstrates the unique capabilities of the multimode Dual Mode Logic (DML) design techniqPalabras claves:Autores:Fish A., Marco Lanuzza, Ramiro Taco, Shavit N., Stanger I.Fuentes:scopusUltra-low-voltage self-body biasing scheme and its application to basic arithmetic circuits
ArticleAbstract: The gate level body biasing (GLBB) is assessed in the context of ultra-low-voltage logic designs. ToPalabras claves:Autores:Albano D., Marco Lanuzza, Ramiro TacoFuentes:scopusRobust dual mode pass logic (DMPL) for energy efficiency and high performance
Conference ObjectAbstract: In the past, Pass Transistor Logic (PTL) was widely used due to benefits in terms of speed and powerPalabras claves:16 nm, dual mode logic (DML), Energy efficiency, Logic family, Low Power, Pass Transistor Logic (PTL)Autores:Fish A., Marco Lanuzza, Ramiro Taco, Shavit N., Stanger I., Yavits L.Fuentes:scopusProcess variation-aware datapath employing dual mode logic
Conference ObjectAbstract: Dual Mode Logic (DML), which was recently introduced by our group, offers the possibility to operatePalabras claves:dual mode logic (DML), Dynamic logic, Process variation, Static cmos, Ultra-low voltageAutores:Fish A., Ramiro Taco, Shavit N., Stanger I.Fuentes:scopusEffects of the technology scaling down to 28nm on Ultra-Low Voltage and Power OTA performance using TCAD simulations
Conference ObjectAbstract: In this paper, the effect on the performances of the technology scaling down to 28nm (bulk and planaPalabras claves:28nm, 90nm, Feed Forward rejection, OTA, PDK, Pseudo Differential Pair, TCAD simulation, Ultra-low power, Ultra-low voltageAutores:André Borja, Juan Orozco, Luis Miguel Procel Moya, Mateo Bonilla, Mateo Valencia, Ramiro Taco, Trojman L.Fuentes:scopus