Mostrando 10 resultados de: 13
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Advances in Intelligent Systems and Computing(3)
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2018 IEEE 3rd Ecuador Technical Chapters Meeting, ETCM 2018(1)
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A Virtual Learning Environments as Training Tools: An Experience with NEO LMS in Physics Teaching
Conference ObjectAbstract: This research shows the design and implementation of a Virtual Learning Environment in Physics at thPalabras claves:e-Learning, NEO LMS, VLEAutores:Juan Polo-Mantuano, Mireya Zapata-RodríguezFuentes:scopusAER-SRT: Scalable spike distribution by means of synchronous serial ring topology address event representation
ArticleAbstract: Given the massive number of interconnects in Spiking Neural Networks (SNNs), distributing spikes effPalabras claves:AER (Address Event Representation), Aurora protocol, Multi-chip communication, SNN emulation, Synchronous serial ring, Time slot emulationAutores:Dorta T., Madrenas J., Mireya Zapata-Rodríguez, Sánchez G.Fuentes:googlescopusCompact associative memory for AER spike decoding in FPGA-based evolvable SNN emulation
Conference ObjectAbstract: A spike decoding scheme for Address Event Representation (AER)-based transmission in Spiking NeuralPalabras claves:AER, Associative memory, Digital neuromorphic systems, Evolvable connections, SNNAutores:Madrenas J., Mireya Zapata-RodríguezFuentes:googlescopusAcceleration of Evolutionary Grammar Using an MISD Architecture Based on FPGA and Petalinuxs
Conference ObjectAbstract: The evolutionary grammars are part of the optimization methods and searching for solutions based onPalabras claves:Evolutionary grammar, Hardware Acceleration, Linux embedded, PetalinuxAutores:Bernardo Vallejo-Mancero, Mireya Zapata-RodríguezFuentes:googlescopusEfficient Configuration for a Scalable Spiking Neural Network Platform by means of a Synchronous Address Event Representation bus
Conference ObjectAbstract: Hardware architectures for Spiking Neural Networks (SNNs) emulation exhibit accelerated processing tPalabras claves:AER (Address Event Representation), Configurability, Fpga, multi-chip platform, PSoC, SNN emulationAutores:Janio Jadán-Guerrero, Madrenas J., Mireya Zapata-RodríguezFuentes:googlescopusEfficient FPGA Implementation of Direct Digital Synthesizer and Digital Up-Converter for Broadband Multicarrier Transmitter
Conference ObjectAbstract: The high performance of FPGA devices allows moving traditionally analog stages into the digital worlPalabras claves:Digital Up-Converter (DUC), Direct Digital Synthesis (DDS), DSP, Fpga, Multi-rate systems, Polyphase structuresAutores:Cristhian Castro, Mireya Zapata-RodríguezFuentes:googlescopusHardware-software co-design for efficient and scalable real-time emulation of SNNs on the edge
Conference ObjectAbstract: This paper introduces a novel workflow for Distributed Spiking Neural Network Architecture (DSNA). APalabras claves:Edge computing, Hardware-Software Integration, HEENS, Neural Computing, SNAVA, SNN, Spiking Neural NetworksAutores:Bernardo Vallejo-Mancero, Madrenas J., Mata-Hernandez D., Mireya Zapata-Rodríguez, Oltra-Oltra J.A., Sato S.Fuentes:googlescopusKinematic optimization of the robot head movements for the evaluation of human-robot interaction in social robotics
Conference ObjectAbstract: This paper presents the simplification of the head movements from the analysis of the biomechanicalPalabras claves:3D additive printing, Biomechanics, Computing engineering, Human robotic interaction, Lightweight mechanical designAutores:Jonathan Salvador Paillacho Corredores, Jorge Rolando Alvarez Tello, Mireya Zapata-RodríguezFuentes:googlescopusNeuropsychological assessment of attention: Symbols and digits test.
ArticleAbstract: Introduction: The symbol digit modality test is a reactive which provides great support in neuropsycPalabras claves:ECUADOR, neuropsychology, SDMT, Symbol Digit Modality Test, University college studentsAutores:Carlos Ramos-Galarza, César Byron Guevara Maldonado, Cesar Guevara, Diego Apolo Buenaño, Janio Jadán-Guerrero, Mireya Zapata-Rodríguez, Pamela Acosta-RodasFuentes:googlescopusPSoC-Based Real-Time Data Acquisition for a Scalable Spiking Neural Network Hardware Architecture
Conference ObjectAbstract: Data acquisition for monitoring the spiky activity of large-scale SNN hardware architectures are a cPalabras claves:data-Acquisition, Monitoring, SOC, Spiking Neural Networks, ZYNQAutores:Balaji U.K., Madrenas J., Mireya Zapata-RodríguezFuentes:googlescopus