Mostrando 10 resultados de: 18
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Solid-State Electronics(4)
2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022(2)
Electronics (Switzerland)(2)
2018 IEEE 3rd Ecuador Technical Chapters Meeting, ETCM 2018(1)
2019 IEEE 4th Ecuador Technical Chapters Meeting, ETCM 2019(1)
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A low-voltage, low-power reconfigurable current-mode softmax circuit for analog neural networks
ArticleAbstract: This paper presents a novel low-power low-voltage analog implementation of the softmax function, witPalabras claves:Activation functions, Deep Neural Networks, Machine learning, SoftmaxAutores:Crupi F., Marco Lanuzza, Strangio S., Tatiana Moposita, Trojman L., Vatalaro M., Vladimirescu A.Fuentes:scopusComparison of Different Technologies for Transistor Rectifiers Circuits for Micropower Energy Harvesters
Conference ObjectAbstract: The present work shows the comparison of planar CMOS, FinFET and Tunnel-FET technologies in the prinPalabras claves:energy harvester, FinFET, full-wave rectifier, planar CMOS, Tunnel-FETAutores:J. Paredes, Luis Miguel Procel Moya, Trojman L.Fuentes:googlescopusAssessment of 10 nm Tunnel-FETs and FinFETs transistors for ultra-low voltage and high-speed digital circuits
Conference ObjectAbstract: The trade-offs of the Tunnel-FETs (TFETs) in terms of delay, energy per cycle, and noise margin arePalabras claves:digital circuits, Energy-delay trade-off, FinFET, Tunnel-FET (TFET), Ultra-low voltageAutores:Christian Cao, Kevin Landázuri, Luis Miguel Procel Moya, Mateo Rendón, Ramiro Taco, Trojman L.Fuentes:scopusAssessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework
ArticleAbstract: This paper explores non-volatile cache memories implemented by spin-transfer torque magnetic randomPalabras claves:cache memory, Device-to-system simulation framework, double-barrier magnetic tunnel junction (DMTJ), FinFET, STT-MRAMAutores:Carpentieri M., Crupi F., Esteban Garzón, Finocchio G., Marco Lanuzza, Rose R.D., Trojman L.Fuentes:scopusAdjusting thermal stability in double-barrier MTJ for energy improvement in cryogenic STT-MRAMs
ArticleAbstract: This paper investigates the impact of thermal stability relaxation in double-barrier magnetic tunnelPalabras claves:77 K, Cryogenic cache, Cryogenic electronics, double-barrier magnetic tunnel junction (DMTJ), STT-MRAM, Thermal stability relaxationAutores:Crupi F., Esteban Garzón, Marco Lanuzza, Rose R.D., Teman A., Trojman L.Fuentes:scopusEffects of the technology scaling down to 28nm on Ultra-Low Voltage and Power OTA performance using TCAD simulations
Conference ObjectAbstract: In this paper, the effect on the performances of the technology scaling down to 28nm (bulk and planaPalabras claves:28nm, 90nm, Feed Forward rejection, OTA, PDK, Pseudo Differential Pair, TCAD simulation, Ultra-low power, Ultra-low voltageAutores:André Borja, Juan Orozco, Luis Miguel Procel Moya, Mateo Bonilla, Mateo Valencia, Ramiro Taco, Trojman L.Fuentes:scopusEfficiency of Double-Barrier Magnetic Tunnel Junction-Based Digital eNVM Array for Neuro-Inspired Computing
ArticleAbstract: This brief deals with the impact of spin-transfer torque magnetic random access memory (STT-MRAM) cePalabras claves:double-barrier magnetic tunnel junction (DMTJ), energy-efficiency, MNIST dataset, multilayer perceptron (MPL), online classification, STT-MRAMAutores:Crupi F., Esteban Garzón, Marco Lanuzza, Tatiana Moposita, Trojman L., Vladimirescu A.Fuentes:scopusExploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs
Conference ObjectAbstract: This paper explores performance and technology-scalability of STT-MRAMs exploiting double-barrier MTPalabras claves:double-barrier magnetic tunnel junction (DMTJ), FinFET, STT-MRAM, technology-voltage scalingAutores:Carpentieri M., Crupi F., Esteban Garzón, Finocchio G., Marco Lanuzza, Rose R.D., Trojman L.Fuentes:scopusEnergy efficient self-adaptive dual mode logic address decoder
ArticleAbstract: This paper presents a 1024-bit self-adaptive memory address decoder based on Dual Mode Logic (DML) dPalabras claves:Address decoder, Controller, Dual mode logic, Self-adaptiveAutores:Ariana Musello, Cristhopher Mosquera, Esteban Garzón, Kevin Vicuña, Luis Miguel Procel Moya, Mateo Rendón, Ramiro Taco, Sara Benedictis, Trojman L.Fuentes:googlescopusEnergy-Efficient FinFET-Versus TFET-Based STT-MRAM Bitcells
Conference ObjectAbstract: This paper explores STT-MRAM bitcells based on double-barrier magnetic tunnel junctions (DMTJs) at tPalabras claves:double-barrier magnetic tunnel junction (DMTJ), FinFET, STT-MRAM, tunnel FET (TFET), Ultralow voltageAutores:Ariana Musello, Luis Miguel Procel Moya, Marco Villegas, Ramiro Taco, Santiago S. Perez, Trojman L.Fuentes:googlescopus