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2018 IEEE 3rd Ecuador Technical Chapters Meeting, ETCM 2018(3)
2019 IEEE 4th Ecuador Technical Chapters Meeting, ETCM 2019(3)
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720p-HD Gray-scale and Color Images Shape Recognition System Implementation on an FPGA Platform with a 1080pFull-HD HDMI Interface using a Hu Moments Algorithm
Conference ObjectAbstract: The present work implements and adapts a fast shape recognition algorithm on the Xilinx VC707 VIRTEXPalabras claves:ADV7511, Fpga, Full-HD, Gray Scale, HDL, HDMI, IIC, RGB, Shape recognitionAutores:André Borja, Daniel Cárdenas, Felipe Toscano, Luis Miguel Procel Moya, Ramiro Taco, Trojman L.Fuentes:scopusA 180 nm Low-Cost Operational Amplifier for IoT Applications
Conference ObjectAbstract: This paper presents the design and post-layout simulation of a two-stage operational amplifier (opamPalabras claves:0.18 μ m, cadence virtuoso, High-performance, internet of things (IoT), Low-cost, miller compensation, operational amplifier, post-layout simulation, stabilityAutores:Ariana Musello, Cristhopher Mosquera, Kevin Vicuña, Luis Miguel Procel Moya, Marco Lanuzza, Mateo Rendón, Ramiro Taco, Trojman L.Fuentes:scopusA Defect-Centric Analysis of the Temperature Dependence of the Channel Hot Carrier Degradation in nMOSFETs
ArticleAbstract: The defect-centric distribution is used to study the temperature dependence of channel hot carrier (Palabras claves:channel hot carrier degradation, defect-centric distribution, temperature analysisAutores:Crupi F., Franco J., Kaczer B., Luis Miguel Procel Moya, Trojman L.Fuentes:googlescopusA Defect-Centric perspective on channel hot carrier variability in nMOSFETs
ArticleAbstract: In this work we confirm the validity of the Defect-Centric distribution for predicting the CHC behavPalabras claves:channel hot carrier degradation, defect-centric distribution, variabilityAutores:Crupi F., Franco J., Kaczer B., Luis Miguel Procel Moya, Trojman L., Tuinhout H., Wils N.Fuentes:googlescopusA low-voltage, low-power reconfigurable current-mode softmax circuit for analog neural networks
ArticleAbstract: This paper presents a novel low-power low-voltage analog implementation of the softmax function, witPalabras claves:Activation functions, Deep Neural Networks, Machine learning, SoftmaxAutores:Crupi F., Marco Lanuzza, Strangio S., Tatiana Moposita, Trojman L., Vatalaro M., Vladimirescu A.Fuentes:scopusA phenomenological model of the resistive switching for Hf-based ReRAM devices
Conference ObjectAbstract: This paper presents the current-voltage (I-V) characteristics of HfO 2 -based Resistive Random AccesPalabras claves:active region, Model, percolation, RERAM, resistive switching, Simulation, stochasticAutores:Laurent Raymond, Silvana Guitarra, Trojman L.Fuentes:googlescopusComparison of Different Technologies for Transistor Rectifiers Circuits for Micropower Energy Harvesters
Conference ObjectAbstract: The present work shows the comparison of planar CMOS, FinFET and Tunnel-FET technologies in the prinPalabras claves:energy harvester, FinFET, full-wave rectifier, planar CMOS, Tunnel-FETAutores:J. Paredes, Luis Miguel Procel Moya, Trojman L.Fuentes:googlescopusAssessment of 10 nm Tunnel-FETs and FinFETs transistors for ultra-low voltage and high-speed digital circuits
Conference ObjectAbstract: The trade-offs of the Tunnel-FETs (TFETs) in terms of delay, energy per cycle, and noise margin arePalabras claves:digital circuits, Energy-delay trade-off, FinFET, Tunnel-FET (TFET), Ultra-low voltageAutores:Christian Cao, Kevin Landázuri, Luis Miguel Procel Moya, Mateo Rendón, Ramiro Taco, Trojman L.Fuentes:scopusAssessment of STT-MRAM performance at nanoscaled technology nodes using a device-to-memory simulation framework
ArticleAbstract: This paper deals with the technology scalability of spin-transfer torque magnetic RAMs (STT-MRAMs)baPalabras claves:Device-to-memory analysis, FinFET, Magnetic tunnel junction (MTJ), STT-MRAM, technology scalingAutores:Crupi F., Esteban Garzón, Marco Lanuzza, Rose R.D., Trojman L.Fuentes:scopusAssessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework
ArticleAbstract: This paper explores non-volatile cache memories implemented by spin-transfer torque magnetic randomPalabras claves:cache memory, Device-to-system simulation framework, double-barrier magnetic tunnel junction (DMTJ), FinFET, STT-MRAMAutores:Carpentieri M., Crupi F., Esteban Garzón, Finocchio G., Marco Lanuzza, Rose R.D., Trojman L.Fuentes:scopus