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Fixed point and power consumption analysis of a coherent receiver for optical access networks implemented in FPGA
Conference ObjectAbstract: We demonstrate an FPGA implementation of the key DSP blocks required for a 10Gb/s coherent receiverPalabras claves:Autores:Daniel Cárdenas, Lavery D., Madan D., Savory S.J., Win S.Fuentes:scopusReducing the power consumption of the CMA equalizer update for a digital coherent receiver
Conference ObjectAbstract: A reduced complexity multiplier-free CMA equalizer update is proposed and synthesized for a 10 Gb/sPalabras claves:Autores:Daniel Cárdenas, Lavery D., Savory S.J., Watts P.Fuentes:scopus