Mostrando 10 resultados de: 10
Filtros aplicados
Publisher
2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019(2)
Solid-State Electronics(2)
IEEE Transactions on Circuits and Systems I: Regular Papers(1)
IEEE Transactions on Nanotechnology(1)
Integration(1)
Área temáticas
Física aplicada(9)
Ciencias de la computación(4)
Instrumentos de precisión y otros dispositivos(2)
Doctrinas(1)
Física(1)
Área de conocimiento
Ingeniería electrónica(5)
Ciencia de materiales(4)
Simulación por computadora(4)
Energía(3)
Origen
scopus(10)
Assessment of STT-MRAM performance at nanoscaled technology nodes using a device-to-memory simulation framework
ArticleAbstract: This paper deals with the technology scalability of spin-transfer torque magnetic RAMs (STT-MRAMs)baPalabras claves:Device-to-memory analysis, FinFET, Magnetic tunnel junction (MTJ), STT-MRAM, technology scalingAutores:Crupi F., Esteban Garzón, Marco Lanuzza, Rose R.D., Trojman L.Fuentes:scopusAssessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework
ArticleAbstract: This paper explores non-volatile cache memories implemented by spin-transfer torque magnetic randomPalabras claves:cache memory, Device-to-system simulation framework, double-barrier magnetic tunnel junction (DMTJ), FinFET, STT-MRAMAutores:Carpentieri M., Crupi F., Esteban Garzón, Finocchio G., Marco Lanuzza, Rose R.D., Trojman L.Fuentes:scopusAn energy aware variation-tolerant writing termination control for STT-based non volatile flip-flops
Conference ObjectAbstract: In this paper, we propose a variation-tolerant design methodology to embed self-write termination coPalabras claves:digital circuits, Energy efficiency, Non-volatile flip-flop, STT-MRAM, VLSI, Zero-leakage circuitsAutores:Alioto M., Crupi F., Marco Lanuzza, Rose R.D.Fuentes:scopusA Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits
ArticleAbstract: In this paper, a variation-aware simulation framework for hybrid circuits comprising MOS transistorsPalabras claves:device-circuit simulation, process variability, Spintronic circuits, stochastic switching, STT-MRAMAutores:Alioto M., Carpentieri M., Crupi F., Finocchio G., Marco Lanuzza, Rose R.D., Siracusano G., Tomasello R.Fuentes:scopusDevice-to-system level simulation framework for STT-DMTJ based cache memory
Conference ObjectAbstract: This paper presents a comparative study on non-volatile cache memories based on nanoscaled spin-tranPalabras claves:Device-to-system simulation framework, Double-barrier magnetic tunnel junction, STT-MRAMAutores:Crupi F., Esteban Garzón, Marco Lanuzza, Rose R.D.Fuentes:scopusAdjusting thermal stability in double-barrier MTJ for energy improvement in cryogenic STT-MRAMs
ArticleAbstract: This paper investigates the impact of thermal stability relaxation in double-barrier magnetic tunnelPalabras claves:77 K, Cryogenic cache, Cryogenic electronics, double-barrier magnetic tunnel junction (DMTJ), STT-MRAM, Thermal stability relaxationAutores:Crupi F., Esteban Garzón, Marco Lanuzza, Rose R.D., Teman A., Trojman L.Fuentes:scopusExploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs
Conference ObjectAbstract: This paper explores performance and technology-scalability of STT-MRAMs exploiting double-barrier MTPalabras claves:double-barrier magnetic tunnel junction (DMTJ), FinFET, STT-MRAM, technology-voltage scalingAutores:Carpentieri M., Crupi F., Esteban Garzón, Finocchio G., Marco Lanuzza, Rose R.D., Trojman L.Fuentes:scopusExploiting STT-MRAMs for Cryogenic Non-Volatile Cache Applications
ArticleAbstract: This paper evaluates the potential of spin-transfer torque magnetic random-access memories (STT-MRAMPalabras claves:77 K, cache memory, cold computing, Cryogenic, STT-MRAMAutores:Crupi F., Esteban Garzón, Marco Lanuzza, Rose R.D., Teman A.Fuentes:scopusImpact of voltage scaling on STT-MRAMs through a variability-aware simulation framework
Conference ObjectAbstract: In this paper, we focus on the study of the impact of voltage scaling on writing performance and enePalabras claves:Magnetic tunnel junction (MTJ), Modeling, STT-MRAM, variability, voltage scalingAutores:Carangelo G., Carpentieri M., Crupi F., Finocchio G., Marco Lanuzza, Rose R.D.Fuentes:scopusRelaxing non-volatility for energy-efficient DMTJ based cryogenic STT-MRAM
ArticleAbstract: Spin-transfer torque magnetic random-access memory (STT-MRAM) is considered as a premiere candidatePalabras claves:77 K, Cryogenic computing, double-barrier magnetic tunnel junction (DMTJ), STT-MRAM, Thermal stability relaxationAutores:Crupi F., Esteban Garzón, Marco Lanuzza, Rose R.D., Teman A., Trojman L.Fuentes:scopus