Esseni D.
40
Coauthors
8
Documentos
Volumen de publicaciones por año
| Año de publicación | Num. Publicaciones |
|---|---|
| 2015 | 1 |
| 2016 | 2 |
| 2017 | 4 |
| 2018 | 1 |
Publicaciones por áreas de conocimiento
| Área de conocimiento | Num. Publicaciones |
|---|---|
| Ingeniería electrónica | 14 |
| Energía | 2 |
| Ingeniería energética | 1 |
Publicaciones por áreas temáticas
| Área temática | Num. Publicaciones |
|---|---|
| Física aplicada | 8 |
| Ciencias de la computación | 2 |
Principales fuentes de datos
| Origen | Num. Publicaciones |
|---|---|
| Scopus | 8 |
| Google Scholar | 0 |
| RRAAE | 0 |
Coautores destacados por número de publicaciones
| Coautor | Num. Publicaciones |
|---|---|
| Strangio S. | 8 |
| Palestri P. | 8 |
| Marco Lanuzza | 8 |
| Crupi F. | 8 |
| Settino F. | 4 |
| Selmi L. | 4 |
Top Keywords
Publicaciones del autor
Early assessment of tunnel-FET for energy-efficient logic circuits
Conference ObjectAbstract: In this paper, we explore the potentialities of TFET-based circuits operating in the ultra-low voltaPalabras claves:Autores:Crupi F., Esseni D., Marco Lanuzza, Palestri P., Strangio S.Fuentes:scopusMixed Tunnel-FET/MOSFET Level Shifters: A New Proposal to Extend the Tunnel-FET Application Domain
ArticleAbstract: In this paper, we identify the level shifter (LS) for voltage up-conversion from the ultralow-voltagPalabras claves:Level shifter (LS), technology computer-Aided design (TCAD), tunnel FET (TFET).Autores:Crupi F., Esseni D., Marco Lanuzza, Palestri P., Strangio S.Fuentes:scopusAssessment of InAs/AlGaSb Tunnel-FET Virtual Technology Platform for Low-Power Digital Circuits
ArticleAbstract: In this work, a complementary InAs/Al0.05Ga0.95Sb tunnel field-effect-Transistor (TFET) virtual techPalabras claves:full-Adder, III-V, tunnel field effect transistor (TFET), very large scale integration (VLSI).Autores:Crupi F., Esseni D., Marco Lanuzza, Palestri P., Selmi L., Strangio S.Fuentes:scopusBenchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits
ArticleAbstract: In this work, a benchmark for low-power digital applications of a III-V TFET technology platform agaPalabras claves:Full adders, III-V, Ripple carry adders, TFETAutores:Crupi F., Esseni D., Marco Lanuzza, Palestri P., Selmi L., Strangio S.Fuentes:scopusA virtual III-V tunnel FET technology platform for ultra-low voltage comparators and level shifters
Conference ObjectAbstract: In this paper, a III-V nanowire TFET technology platform is compared against the pbkp_redictive techPalabras claves:comparator, hybrid design, level shifter, TFETAutores:Crupi F., Esseni D., Marco Lanuzza, Palestri P., Settino F., Strangio S.Fuentes:scopus