Mostrando 10 resultados de: 21
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Energy Procedia(2)
Journal of Low Power Electronics(2)
Proceedings - IEEE International Symposium on Circuits and Systems(2)
2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019(1)
IEEE 4th International Forum on Research and Technologies for Society and Industry, RTSI 2018 - Proceedings(1)
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Ciencias de la computación(15)
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Assessment of STT-MRAM performance at nanoscaled technology nodes using a device-to-memory simulation framework
ArticleAbstract: This paper deals with the technology scalability of spin-transfer torque magnetic RAMs (STT-MRAMs)baPalabras claves:Device-to-memory analysis, FinFET, Magnetic tunnel junction (MTJ), STT-MRAM, technology scalingAutores:Crupi F., Esteban Garzón, Marco Lanuzza, Rose R.D., Trojman L.Fuentes:scopusAssessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework
ArticleAbstract: This paper explores non-volatile cache memories implemented by spin-transfer torque magnetic randomPalabras claves:cache memory, Device-to-system simulation framework, double-barrier magnetic tunnel junction (DMTJ), FinFET, STT-MRAMAutores:Carpentieri M., Crupi F., Esteban Garzón, Finocchio G., Marco Lanuzza, Rose R.D., Trojman L.Fuentes:scopusA comparative study of MWT architectures by means of numerical simulations
Conference ObjectAbstract: In order to improve the efficiency of c-Si and mc-Si solar cells, Metal Wrap Though (MWT) architectuPalabras claves:back contact, MWT, numerical simulation, Photovoltaics, Solar cell, VíaAutores:Crupi F., Fiegna C., Frei M., Magnone P., Marco Lanuzza, Rose R.D., Sangiorgi E., Tonini D.Fuentes:scopusA variation-aware simulation framework for hybrid CMOS/spintronic circuits
Conference ObjectAbstract: In this paper, a variation-aware simulation framework is introduced for hybrid circuits comprising MPalabras claves:device-circuit simulation, magnetic memory, Spintronic circuits, variationsAutores:Alioto M., Carpentieri M., Crupi F., Finocchio G., Marco Lanuzza, Rose R.D., Siracusano G., Tomasello R.Fuentes:scopusDevice-to-system level simulation framework for STT-DMTJ based cache memory
Conference ObjectAbstract: This paper presents a comparative study on non-volatile cache memories based on nanoscaled spin-tranPalabras claves:Device-to-system simulation framework, Double-barrier magnetic tunnel junction, STT-MRAMAutores:Crupi F., Esteban Garzón, Marco Lanuzza, Rose R.D.Fuentes:scopusDesign and evaluation of an energy-delay-area efficient datapath for coarse-grain reconfigurable computing systems
ArticleAbstract: This paper presents the architecture and complete VLSI implementation of a high data throughput, enePalabras claves:arithmetic circuits, Data path design, Reconfigurable architecturesAutores:Corsonello P., Marco Lanuzza, Margate M., Perri S., Purohit S.Fuentes:scopusDesign and evaluation of high-speed energy-aware carry skip adders
Conference ObjectAbstract: In this paper, the impact of different dynamic logic design styles is evaluated considering as benchPalabras claves:Autores:Frustaci F., Marco Lanuzza, Rose R.D.Fuentes:scopusDesign of energy aware adder circuits considering random intra-die process variations
ArticleAbstract: Energy consumption is one of the main barriers to current high-performance designs. Moreover, the inPalabras claves:Adder design, Intra-die process variations, Yield-driven designAutores:Corsonello P., Frustaci F., Marco Lanuzza, Perri S.Fuentes:scopusDesign space exploration of split-path data driven dynamic full adder
ArticleAbstract: This paper presents the design, the analysis and the complete characterization of a novel split-pathPalabras claves:arithmetic circuits, Full Adder, Split-Path D3LAutores:Marco Lanuzza, Margala M., Purohit S.Fuentes:scopusExtended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology
Conference ObjectAbstract: Recently, we proposed a low-granularity back-bias control technique [1] optimized for the ultra-thinPalabras claves:28nm UTBB FD-SOI, Dynamic body biasing, low voltage designAutores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopus