Mostrando 9 resultados de: 9
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Publisher
2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022(2)
2019 IEEE 4th Ecuador Technical Chapters Meeting, ETCM 2019(1)
ETCM 2021 - 5th Ecuador Technical Chapters Meeting(1)
Integration(1)
Latin American Electron Devices Conference, LAEDC 2019(1)
Área de conocimiento
Ingeniería electrónica(7)
Ciencia de materiales(3)
Fabricación de dispositivos semiconductores(3)
Energía(2)
Simulación por computadora(2)
Comparison of Different Technologies for Transistor Rectifiers Circuits for Micropower Energy Harvesters
Conference ObjectAbstract: The present work shows the comparison of planar CMOS, FinFET and Tunnel-FET technologies in the prinPalabras claves:energy harvester, FinFET, full-wave rectifier, planar CMOS, Tunnel-FETAutores:J. Paredes, Luis Miguel Procel Moya, Trojman L.Fuentes:googlescopusAssessment of 10 nm Tunnel-FETs and FinFETs transistors for ultra-low voltage and high-speed digital circuits
Conference ObjectAbstract: The trade-offs of the Tunnel-FETs (TFETs) in terms of delay, energy per cycle, and noise margin arePalabras claves:digital circuits, Energy-delay trade-off, FinFET, Tunnel-FET (TFET), Ultra-low voltageAutores:Christian Cao, Kevin Landázuri, Luis Miguel Procel Moya, Mateo Rendón, Ramiro Taco, Trojman L.Fuentes:scopusAssessment of STT-MRAM performance at nanoscaled technology nodes using a device-to-memory simulation framework
ArticleAbstract: This paper deals with the technology scalability of spin-transfer torque magnetic RAMs (STT-MRAMs)baPalabras claves:Device-to-memory analysis, FinFET, Magnetic tunnel junction (MTJ), STT-MRAM, technology scalingAutores:Crupi F., Esteban Garzón, Marco Lanuzza, Rose R.D., Trojman L.Fuentes:scopusAssessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework
ArticleAbstract: This paper explores non-volatile cache memories implemented by spin-transfer torque magnetic randomPalabras claves:cache memory, Device-to-system simulation framework, double-barrier magnetic tunnel junction (DMTJ), FinFET, STT-MRAMAutores:Carpentieri M., Crupi F., Esteban Garzón, Finocchio G., Marco Lanuzza, Rose R.D., Trojman L.Fuentes:scopusExploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs
Conference ObjectAbstract: This paper explores performance and technology-scalability of STT-MRAMs exploiting double-barrier MTPalabras claves:double-barrier magnetic tunnel junction (DMTJ), FinFET, STT-MRAM, technology-voltage scalingAutores:Carpentieri M., Crupi F., Esteban Garzón, Finocchio G., Marco Lanuzza, Rose R.D., Trojman L.Fuentes:scopusEnergy-Efficient FinFET-Versus TFET-Based STT-MRAM Bitcells
Conference ObjectAbstract: This paper explores STT-MRAM bitcells based on double-barrier magnetic tunnel junctions (DMTJs) at tPalabras claves:double-barrier magnetic tunnel junction (DMTJ), FinFET, STT-MRAM, tunnel FET (TFET), Ultralow voltageAutores:Ariana Musello, Luis Miguel Procel Moya, Marco Villegas, Ramiro Taco, Santiago S. Perez, Trojman L.Fuentes:googlescopusTFET and FinFET Hybrid Technologies for SRAM Cell: Performance Improvement over a Large VDD-Range
Conference ObjectAbstract: This work proposes and compares Static Random-Access Memory (SRAM) cells using hybrid technology forPalabras claves:CMOS, DELAY, FinFET, hybrid, Power consumption, SRAM, Static Noise Margin, TFET, Write Noise MarginAutores:Adriana Arevalo, Liautard R., Luis Miguel Procel Moya, Trojman L.Fuentes:googlescopusNew Insight for next Generation SRAM: Tunnel FET versus FinFET for Different Topologies
Conference ObjectAbstract: The purpose of this work is to point out the main differences between a Static Random-Access MemoryPalabras claves:FinFET, Low voltage, SRAM memory, stability analysis, Static Noise Margins, Tunnel-FETAutores:Adriana Arevalo, Daniel Romero, Liautard R., Luis Miguel Procel Moya, Trojman L.Fuentes:scopusVoltage and Technology Scaling of DMTJ-based STT-MRAMs for Energy-Efficient Embedded Memories
Conference ObjectAbstract: This work presents energy advantages allowed by the technology and voltage scaling of spin-transferPalabras claves:double-barrier magnetic tunnel junction (DMTJ), Embedded memory, energy-efficient, FinFET, Low-voltage, STT-MRAMAutores:Esteban Garzón, Luis Miguel Procel Moya, Marco Lanuzza, Ramiro Taco, Trojman L.Fuentes:scopus